1. Field of the Invention
The present invention relates to a stacked module including multiple wiring boards that are layered in a vertical direction, a stacked module in which each layer of the wiring boards can be precisely connected, and a manufacturing method thereof.
2. Description of the Related Art
In general, technology of this type has been disclosed in Japanese Unexamined Patent Application Publication No. 7-263625 (Patent Document 1), Japanese Unexamined Patent Application Publication No. 8-236694 (Patent Document 2, Japanese Unexamined Patent Application Publication No. 11-8474 (Patent Document 3), and Japanese Unexamined Patent Application Publication No. 11-251515 (Patent Document 4).
In Patent Document 1, a vertical layered IC chip article is disclosed which includes a discrete chip carrier made of a dielectric tape. This layered IC chip article includes a substrate including multiple fused dielectric tape layers and a hollow space defined by an opening in the upper tape layer, wherein the IC chip is disposed in the hollow space. The layered IC chip article also includes a horizontal wiring path provided on the substrate along one or more of the tape layers, a vertical wiring path which passes through the uppermost tape layer on the substrate and extends toward the horizontal wiring path, an electric connecting unit for connecting the IC chip to the vertical wiring path, a carrier mutual connecting unit for connecting between the vertical wiring paths for adjacent carriers, and a layered connecting unit which connects each carrier mutual connecting unit for performing external connections, for example, to a layered article. Thus, the amount of used surface area is reduced, the advantages of an LTCC configuration are maintained, a standard IC chip can be used, and a 3-dimensional IC chip layered article can be obtained in which substandard chips can be replaced without destroying the other chips of the layered article.
In Patent Document 2, a semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes multiple layered carriers, said carriers having a through hole in the inner side or end surface, a conductor pattern provided on at least the surface of the carrier, an inner bonding pad which is electrically connected to the through hole provided on the end surface of the carrier, and LSI chips which are connected and fixed by the inner bonding pad, and which are also connected three-dimensionally with the through hole portion. Thus, a stacked module semiconductor package is obtained which is small, thin, and highly precise, and which has extremely short wiring lengths and good electrical properties, and which is also low-cost and highly reliable, without using wire bonding or TAB methods.
In Patent Document 3, a manufacturing method of a multi-layer board is disclosed. This manufacturing method includes a step of providing multiple boards each having electrode pads with semiconductor chips mounted on the front surface and back surface thereof, a step of layering multiple boards by narrowing the soldering member for connecting between the electrode pads of each board, and a step of heating the layered board and melting the connector soldering member to connect each board. Thus, by performing the heating process only one time, the connection reliability between the semiconductor chips and the boards is improved, the manufacturing time is decreased, and the productivity is increased.
In Patent Document 4, a layered semiconductor device module is disclosed in which thermal stress is reduced. With this layered semiconductor device module, a resin fills the spaces between the circuit boards which are made of differing materials, a printed board that functions as a dummy board is layered between the bottom-most ceramic board and a mounting printed board, under a module, and a resin also fills a space between this dummy board and the bottom-most layer of ceramic board. Thus, the terminal stress of the connecting point of the connecting portion between the ceramic board and the printed board adjacent to a BGA-type layered semiconductor device module is eased between the bottom-most layer of ceramic board and the printed wiring board for mounting the module, thereby enabling many variations of circuit board combinations as well as a larger board.
However, with a conventional stacked module manufacturing method, a soldering ball with a Cu core or a sphere-shaped metal is used as the connecting bump between the boards. Therefore, the adhesion members, such as the spheres, cannot be processed at one time as is the case with a printed paste, but rather, the spheres must be disposed one at a time, or a specialized collet must be used for disposing the spheres. Further, in order to prevent the disposed soldering balls from shifting positions, a soldering paste or flax must be provided to fix the sphere-shaped adhesive members beforehand. Therefore, when connecting the boards to one another, the manufacturing processes for forming a connecting bump as described above increase substantially, and since a large amount of time and effort are required, the product cost and the rate of defective goods are increased. With Patent Document 3, the process is simplified by reducing the heat processing from twice to once. However, the processes for painting flax on the surface electrode and for disposing the soldering ball are still required. Thus, from the perspective of the complication of the process, this is no different from the technologies disclosed in the other Patent Documents. In addition, because of the complications involved in the process, a region in the vicinity of the soldering balls must be provided in which certain components cannot be mounted, which prevents the size of the product from being sufficiently reduced.